Performance Analysis of VLSI Floor planning using Evolutionary Algorithm
P Sivaranjani and K K Kawya. Article: Performance Analysis of VLSI Floor planning using Evolutionary Algorithm. IJCA Proceedings on International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences ICIIIOES(9):42-46, December 2013. Full text available. BibTeX
@article{key:article,
author = {P. Sivaranjani and K. K. Kawya},
title = {Article: Performance Analysis of VLSI Floor planning using Evolutionary Algorithm},
journal = {IJCA Proceedings on International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences},
year = {2013},
volume = {ICIIIOES},
number = {9},
pages = {42-46},
month = {December},
note = {Full text available}
}
Abstract
Floorplanning is an important physical design step for hierarchical, building-block design methodology. When the circuit size get increases the complexity of the circuit also increases. To deal with the increasing design complexity the intellectual property (IP) modules are mostly used in floorplanning. This paper presents a Hybrid particle swarm optimization algorithm for floorplanning optimization. Here B*tree is used at the initial stage in order to avoid overlapping of modules and later, PSO algorithm along with the concept of crossover and mutation from Genetic algorithm is used to get optimal placement solution. The main objective of floorplanning is to minimize the chip area and interconnection wire length. The Experimental results on Microelectronic Center of North Carolina (MCNC) benchmark circuits shows that our algorithm performs better convergence than the other methods.
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