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Implementation of on Chip Data Bus Using Pre Emphasis Signaling
IJCA Special Issue on Optimization and On-chip Communication
© 2012 by IJCA Journal
ooc - Number 1
Year of Publication: 2012
Pallavi Dedge and S C Badwaik. Article: Implementation of on Chip Data Bus Using Pre Emphasis Signaling. IJCA Special Issue on Optimization and On-chip Communication ooc(1):32-39, February 2012. Full text available. BibTeX
@article{key:article,
author = {Pallavi Dedge and S.C. Badwaik},
title = {Article: Implementation of on Chip Data Bus Using Pre Emphasis Signaling},
journal = {IJCA Special Issue on Optimization and On-chip Communication},
year = {2012},
volume = {ooc},
number = {1},
pages = {32-39},
month = {February},
note = {Full text available}
}
Abstract
This work describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25- ? m complementary metal–oxide–semi- conductor (CMOS) technology attains an aggregate signaling data rate of 64 Gb/s over 5–10-mm-long lossy interconnects. With a supply of 2.5 V, 25.5–48.7-mW power dissipation
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