Performance Evaluation of Traffic Permutations for Mesh On-Chip Networks
Naveen Choudhary, Dharm Singh and Abhilasha Sharma. Article: Performance Evaluation of Traffic Permutations for Mesh On-Chip Networks. IJCA Special Issue on Optimization and On-chip Communication ooc(1):6-10, February 2012. Full text available. BibTeX
@article{key:article,
author = {Naveen Choudhary and Dharm Singh and Abhilasha Sharma},
title = {Article: Performance Evaluation of Traffic Permutations for Mesh On-Chip Networks},
journal = {IJCA Special Issue on Optimization and On-chip Communication},
year = {2012},
volume = {ooc},
number = {1},
pages = {6-10},
month = {February},
note = {Full text available}
}
Abstract
Networks-on-Chip (NoC) is recently proposed as an alternative to the on-chip bus to meet the increasing requirement of complex communication needs in Systems-on-Chip (SoC). Using on-chip interconnection networks in place of ad-hoc global wiring, structures the top level wires on a chip and facilitates modular design. The structured network wiring gives well-controlled electrical parameters that eliminate timing iterations and enable the use of high-performance circuits to reduce latency and increase bandwidth. Using a network to replace global wiring has advantages of structure, performance, and modularity. With this approach, system modules (processors, memories, peripherals, etc.) communicate by sending packets to one another over the network. In NoC, nodes are arranged in the topology such that communication between any nodes is possible even though they are not directly connected. Each node is a IP core which can be a DSP, Microprocessor, Memory along with routing function which is responsible for forwarding the data packet to the neighboring node.
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