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Hardware Implementation of Mix Column Step in AES
IJCA Special Issue on Communication and Networks
© 2011 by IJCA Journal
comnetcn - Number 1
Year of Publication: 2011
Pratap Kumar Dakua, Manoranjan Pradhan and Subba Rao Polamuri. Article: Hardware Implementation of Mix Column Step in AES. IJCA Special Issue on Communication and Networks comnetcn(1):6-9, December 2011. Full text available. BibTeX
@article{key:article,
author = {Pratap Kumar Dakua and Manoranjan Pradhan and Subba Rao Polamuri},
title = {Article: Hardware Implementation of Mix Column Step in AES},
journal = {IJCA Special Issue on Communication and Networks},
year = {2011},
volume = {comnetcn},
number = {1},
pages = {6-9},
month = {December},
note = {Full text available}
}
Abstract
This document gives the hardware implementation of Mix Column step in AES encryption process. The AES encryption process consists of several transformation steps such as byte substitution, shift rows, mix column and addition of round key operation step. There are two aspects to perform mix column step in AES is presented. The total operation is coded with VERILOG, synthesized and simulated using Xilinx ISE 10.1.
References
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- NIST: Specification for the Advanced Encryption Standard (AES). Technical Report FIPS PUB 197, National Institute of Standards and Technology (NIST) (2001.
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- Tilborg, Henk C.A.van., Fundamentals of Cryptography: A Professional Reference and Interactive Tutorial, New York. Kluwer Academic publishers, 2002.