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Performance Comparison of an Algorithmic Current-Mode ADC Implemented using Different Current Comparators
IJCA Proceedings on Recent Trends in Electronics and Communication 2013
© 2013 by IJCA Journal
RTEC
Year of Publication: 2013
Veepsa Bhatia, Neeta Pandey and Asok Bhattacharyya. Article: Performance Comparison of an Algorithmic Current-Mode ADC Implemented using Different Current Comparators. IJCA Proceedings on Recent Trends in Electronics and Communication 2013 RTEC:14-18, December 2013. Full text available. BibTeX
@article{key:article,
author = {Veepsa Bhatia and Neeta Pandey and Asok Bhattacharyya},
title = {Article: Performance Comparison of an Algorithmic Current-Mode ADC Implemented using Different Current Comparators},
journal = {IJCA Proceedings on Recent Trends in Electronics and Communication 2013},
year = {2013},
volume = {RTEC},
pages = {14-18},
month = {December},
note = {Full text available}
}
Abstract
In this paper a 4-bit algorithmic current mode Analog-to-Digital Converter (ADC) has been implemented. A vital component of this ADC is a current comparator. We have simulated three popular structures of current comparators that can be used to implement this ADC and compared their performance. The circuit has been implemented using 0. 18 ?m CMOS technology with a supply voltage of 1. 8V.
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