A High Speed CMOS Current Comparator in 90 nm CMOS Process Technology
Adyasha Rath, Sushanta K Mandal, Subhrajyoti Das and Sweta Padma Dash. Article: A High Speed CMOS Current Comparator in 90 nm CMOS Process Technology. IJCA Proceedings on International Conference on Microelectronics, Circuits and Systems MICRO(2):1-5, October 2014. Full text available. BibTeX
@article{key:article,
author = {Adyasha Rath and Sushanta K. Mandal and Subhrajyoti Das and Sweta Padma Dash},
title = {Article: A High Speed CMOS Current Comparator in 90 nm CMOS Process Technology},
journal = {IJCA Proceedings on International Conference on Microelectronics, Circuits and Systems},
year = {2014},
volume = {MICRO},
number = {2},
pages = {1-5},
month = {October},
note = {Full text available}
}
Abstract
In this paper a current mode comparator is presented, more aptly can be called as the "Current Comparator". The proposed circuit consists of a current differencing stage which accepts two current inputs where one is the reference current and the other is the input current. The comparator stage outputs a rail-to-rail voltage depending on the difference of the two currents. Simulation of the proposed design is carried out in Cadence using EDA tool in 90nm technology. The operating speed of the current comparator was found to be 1. 82GHz with an average power dissipation of 122µW. The high speed operation was confirmed by the transient analysis results in which the delay was found to be 0. 55ns at an input current difference of ±1µA.
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