Modified Double-Edge Triggered Clock Branch Sharing Architecture for Ultra Low Power Design
Komal Priyadarshini and Srinibasa Padhy. Article: Modified Double-Edge Triggered Clock Branch Sharing Architecture for Ultra Low Power Design. IJCA Proceedings on International Conference on Microelectronics, Circuits and Systems MICRO(1):24-27, October 2014. Full text available. BibTeX
@article{key:article,
author = {Komal Priyadarshini and Srinibasa Padhy},
title = {Article: Modified Double-Edge Triggered Clock Branch Sharing Architecture for Ultra Low Power Design},
journal = {IJCA Proceedings on International Conference on Microelectronics, Circuits and Systems},
year = {2014},
volume = {MICRO},
number = {1},
pages = {24-27},
month = {October},
note = {Full text available}
}
Abstract
Power consumption plays an essential role in VLSI design. Earlier, the VLSI designers were more concentrated on performance and area, but, gradually, low power consumption became one of the most important factors in VLSI design. Increasing demand and growth of portable devices have increased the demand of power efficient VLSI circuits. In this paper, various conventional low power designs are analyzed and a low power double-edge triggered flip-flop using clock branch sharing technique along with MTCMOS and Voltage Scaling technique has been proposed. All the simulations have been carried out using Cadence EDA tools in 0. 18 µm technology at room temperature. The power consumption has reduced significantly as compared to earlier techniques.
References
- J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 2003.
- N. Weste and D. Harris, CMOS VLSI Design. Reading, MA:Addison Wesley, 2004.
- H. Kawaguchi and T. Sakurai, "A reduced clock-swing flip-flop (RCSFF) for 63% power reduction," IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 807–811, May 1998.
- M. Kang, Y. Leblebici, CMOS Digital Integrated Circuits, 3rd ed. 2003, pp. 452-454.
- P. Dobriyal, K. Sharma, M. Sethi, G. Sharma, "A High Performance D-Flip Flop Design with Low Power Clocking System using MTCMOS Technique," Advance Computing Conference (IACC), 2013 IEEE 3rd International.
- W. Chung, T. Lo, and M. Sachdev, "A comparative analysis of low power low-voltage dual-edge-triggered flip-flops," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 10, no. 6, pp. 913–918, Dec. 2002.
- J. Tschanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev, and V. De, "Comparative delay and energy of single edge-triggered and dual edgetriggered pulsed flip-flops for high-performance microprocessors," in Proc. ISPLED, 2001, pp. 207–212.
- N. Nedovic´ and V. G. Oklobd?zija, "Dual-edge triggered storage elements and clocking strategy for low-power systems," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 13, no. 5, pp. 577–590, May 2005.
- P. Zhao, T. Darwish, and M. Bayoumi, "Low power and high speed explicit-pulsed flip-flops," in Proc. 45th IEEE Int. Midw. Symp. Circuits Syst. Conf. , 2002, pp. 477–480
- Y. -Y. Sung and R. C. Chang, "A novel CMOS double-edge triggered flip-flop for low-power applications," in Proc. IEEE Int. Symp. Circuits Syst. , May 2004, pp. 665–668
- C. L. Kim and S. Kang, "A low-swing clock double edge-triggered flip-flop," IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 648 652, May 2002.
- V. Stojanovic and V. Oklobdzija, "Comparative analysis of master–slave latches and flip-flops for high-performance and low power system," IEEE J. Solid State Circuits, vol. 34, no. 4, pp. 536–548, Apr. 1999.
- J. Tschanz, K. Bowman, and V. De, "Variation-tolerant circuits: Circuits solutions and techniques," in Proc. IEEE Symp. Des. Autom. Conf. , 2005, pp. 762-763.
- P. Zhao, Jason McNeely, P. Golconda, M. Bayoumi, R. Barcenas, W. Kuang, " Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop," IEEE transactions on very large scale integration (VLSI) systems, vol. 15, no. 3, march 2007.