UART Designing for Four Different Baud Rate for Cyclone III Family
Sunita Satyaram Yadav, Asha Durafe and Pratik Kanani. Article: UART Designing for Four Different Baud Rate for Cyclone III Family. IJCA Proceedings on International Conference and Workshop on Emerging Trends in Technology 2014 ICWET 2014(2):30-33, May 2013. Full text available. BibTeX
@article{key:article,
author = {Sunita Satyaram Yadav and Asha Durafe and Pratik Kanani},
title = {Article: UART Designing for Four Different Baud Rate for Cyclone III Family},
journal = {IJCA Proceedings on International Conference and Workshop on Emerging Trends in Technology 2014},
year = {2013},
volume = {ICWET 2014},
number = {2},
pages = {30-33},
month = {May},
note = {Full text available}
}
Abstract
UART (Universal Asynchronous Receiver Transmitter) is used for short-distance, low speed, low-cost data exchange between computer and peripheral. They provide a means to send data with a minimum of wires. The data is sent bit-serially, and no clock signal is sent along with it. The fact that a clock is not transmitted with the data complicates the design of a UART. The two systems (sender and receiver) have separate, unsynchronized, clock signals. The programmable logic devices can be used for such application by developing core for UART. By using hardware descriptive language UART simulation can be tested before it can be loaded on programmable device. In this project we present UART which includes three modules which are the baud rate generator, receiver and transmitter.
References
- Biplab Roy," Platform-Independent Customizable UART Soft-Core", Third International Conference on Intelligent Systems Modelling and Simulation, 2012.
- Dr. Garima Bandhawarkar Wakhle, Iti Aggarwal and Shweta Gaba," Synthesis and Implementation of UART using VHDL Codes", International Symposium on Computer, Consumer and Control, 2012.
- A. R. M. Khan, A. P. Thakare," FPGA based design & implementation of serial data transmission controller", International Journal of Engineering Science and Technology Vol. 2(10), 2010, 5526-5533.
- Amanpreet Kaur, Amandeep Kaur," An Approach For Designing A Universal Asynchronous Receiver Transmitter (UART)", International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622, Vol. 2, Issue 3, May-Jun 2012, pp. 2305-2311.
- Lab 7,"UART Design",University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences, EECS 150 Spring 2002.
- Ms. Krupa Joshi, Dipak Patel, Chintan Patel, Rahul Kher, Design and Simulation of UART IP Core for FPGA Implementation, National Conference on Recent Trends in Engineering & Technology, 13-14 May 2011.
- B. JEEVAN ,M. NEERAJA, Design and simulation of UART protocol based on verilog, International Conference on Electronics and Communication Engineering (ICECE) -16th Sept, 2012, Pune- ISBN: 978-93-82208-18-1.