Performance Analysis of 4-bit Flash ADC with Different Comparators Designed in 0. 18um Technology
A Nandhini, M Shanthi and M C Bhuvaneswari. Article: Performance Analysis of 4-bit Flash ADC with Different Comparators Designed in 0.18um Technology. IJCA Proceedings on International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences ICIIIOES(5):1-5, December 2013. Full text available. BibTeX
@article{key:article,
author = {A. Nandhini and M. Shanthi and M. C. Bhuvaneswari},
title = {Article: Performance Analysis of 4-bit Flash ADC with Different Comparators Designed in 0.18um Technology},
journal = {IJCA Proceedings on International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences},
year = {2013},
volume = {ICIIIOES},
number = {5},
pages = {1-5},
month = {December},
note = {Full text available}
}
Abstract
This paper concerns the design of Flash type of Analog to Digital Converter (ADC) which is more likely to be used for high quality audio and video signals. It uses resistor ladder logic, comparator and encoder to convert the continuous input signal into binary form. Comparator, encoder circuits are designed using CMOS technology and its output response is obtained to meet the requirements. Comparators form the main element to design Flash ADC. Different architectures of comparators are designed to build 4 bit Flash ADC. Dynamic characteristics of the converter are analyzed and its performance is compared with different comparator architecture. Design of these circuit use gpdk 180nm technology in cadence tool and simulated using SPECTRE.
References
- Pradeep Kumar, Amit Kolhe, 2011" Design & Implementation of Low Power 3-bitFlash ADC in 0. 18?m CMOS", International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-1, Issue-5.
- P. Rajeswari, R. Ramesh, A. R. Ashwatha 2012," An approach to design Flash Analog to Digital Converter for High Speed and Low power Applications", International Journal of VLSI design & Communication Systems (VLSICS) Vol. 3, No. 2.
- M Suresh, Santoshi Sahu, Kiran Sadangi and A K Panda 2009," A Novel Flash Analog-to-Digital Converter Design using Cadence Tool", 978-0-7695-3845-7/09 IEEE computer society
- Channakka Lakkannavar, Shrikanth K, Kalmeshwar. N, (2012)" Design implementation and analysis of Flash ADC architecture with differential amplifier as comparator using CD approach", International Journal of Electronics Signals and Systems (IJESS) ISSN: 2231- 5969, Vol-1 Iss-3.
- Rahul Moud,D. B. Ojha, 2012" Design of Chip for Flash ADC application of MCML in 180nm Technology", Journal of Computing Technologies ISSN 2278 – 3814,volume1.
- Chia-Nan Yeh and Yen-Tai Lai 2008, "A Novel Flash Analog- to-Digital Converter," 978-1-4244-1684-4/08 © IEEE.
- Mingzhen Wang, 2007" High-Speed Low-Power Cmos Flash Analog-To-Digital Converter For Wideband Communication System-On-A-Chip", Ph. D Thesis, Wright State University.
- Shubhara Yewale, Radheshyam Gamad, 2012" Design of Low Power and High Speed CMOS Comparator for A/D Converter Application", Wireless Engineering and Technology, , 3, 90-95
- Vipul Katyal, 2008" Low power high speed and high accuracy design methodologies for Pipeline Analog-to-Digital converters", Ph. D Thesis, Iowa State University.
- H. Gupta and B. Ghosh, 2012" Analog Circuits Design Using Ant Colony Optimization", IJECCT, Vol. 2 (3)
- HeungJun Jeon," Low-power high-speed low-offset fully dynamic CMOS latched comparator", 978-1-4244-6682-5, 2010, IEEE conference publications.
- R. Jacob Baker, Harry W. Li, David E. Boyce, "CMOS Circuit Design Layout and Simulation," ISBN 0-7803- 3416-7, IEEE Press, 445 Hose Lane, P. O. Box 1331, NJ08855-1331 USA
- P. E. Allen & D. R. Holberg, "CMOS Analog Circuit Design, Second Edition", Oxford University Press.