A Heuristic Approach for VLSI Floorplanning
Rajalakshmi. P and Senojjoseph. Article: A Heuristic Approach for VLSI Floorplanning. IJCA Proceedings on International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences ICIIIOES(13):1-6, December 2013. Full text available. BibTeX
@article{key:article,
author = {Rajalakshmi. P and Senojjoseph},
title = {Article: A Heuristic Approach for VLSI Floorplanning},
journal = {IJCA Proceedings on International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences},
year = {2013},
volume = {ICIIIOES},
number = {13},
pages = {1-6},
month = {December},
note = {Full text available}
}
Abstract
Floorplanning is an essential step in VLSI chip design automation. The main objective of the floorplanning is to find a floorplan such that the cost is minimized. This is achieved by minimizing the chip area and interconnection cost. It determines the performance, size, yield and reliability of VLSI chips. We propose a Memetic Algorithm (MA) for non-slicing and hard module VLSI floorplanning problem. This MA is a hybrid genetic algorithm that uses effective genetic search method to explore the search space and an efficient local search method to exploit information in the search region. The exploration and exploitation are balanced by threshold bias search strategy. MA works better than the existing algorithms and is efficient, faster and cost effective algorithm. A better floorplan with minimal chip area and interconnection cost will be obtained using the MA for non-slicing and hard module VLSI floorplanning problem. MA is mainly used to produce optimal or near optimal solution. The experimental results are analyzed to check the performance of MA.
References
- Maolin Tang and Xin Yao, "A Memetic Algorithm for VLSI Floorplanning", IEEE transactions on systems, man, and cybernetics—part b: cybernetics, VOL. 37, NO. 1, 2007, pp. 62-69.
- Pei-Ning Guo, Toshihiko Takahashi, Chung-Kuan Cheng, "Floorplanning Using a Tree Representation", IEEE transactions on computer-aided design of integrated circuits and systems, VOL. 20, NO. 2, 2001, pp. 281-289.
- Christine L. Valenzuela and Pearl Y. Wang, "A Genetic Algorithm for VLSI Floorplanning".
- M. Rebaudengo and M. Reorda, "GALLO: A genetic algorithm for floorplan area optimization," IEEE Trans. Comput. -Aided Design Integr. Circuits Syst. , vol. 15, no. 8, pp. 943–951, Aug. 1996
- J. Cohoon, S. Hegde, W. Martin, and D. Richards, "Distributed genetic algorithms for the floorplan design problem," IEEE Trans. Comput. -Aided Design Integr. Circuits Syst. , vol. 10, no. 4, pp. 483–492, Apr. 1991.
- H. Ishibuchi, T. Yoshida, and T. Murata, 2003 "Balance between genetic search and local search in memetic algorithms for multiobjective permutation flowshop scheduling,"
- Sabih H. Gerez, "Algorithms for VLSI Design Automation", John Wiley & Sons Inc. , U. K, Second Edition.
- Naveed Sherwani, "Algorithms for VLSI Design Automation", John Wiley & Sons Inc. , U. K, Second Edition.
- Anuradha A. Puntambekar, "Data Structures", Technical Publications, Pune.
- Michael John Sebastian Smith, "Application Specific Integrated Circuits", Pearson Edition.
- Maolin Tang, Raymond Y. K. Lau," A Parallel Genetic Algorithm for Floorplan Area Optimization", Seventh International Conference on Intelligent Systems Design and Applications,IEEE, 2007, pp. 801-806
- Guolong Chen, Wenzhong Guo, Yuzhong Chen, "A PSO-based intelligent decision algorithm for VLSI Floorplanning", Soft Computing, VOL. 14, NO. 12, Springer, 2009, pp. 1329-1337.
- Jianli Chen, Wenxing Zhu, and M. M. Ali, "A Hybrid Simulated Annealing Algorithm for Nonslicing VLSI Floorplanning", IEEE transactions on systems, man and cybernetics—part c: applications and reviews, VOL. 41, NO. 4, 2011, pp. 544-553.
- Guolong Chen, Wenzhong Guo, Yuzhong Chen, "A PSO-based intelligent decision algorithm for VLSI floorplanning", Springer, Soft Computing, 2010, pp. 1329–1337.
- C. Valenzuela and P. Wang, "VLSI placement and area optimization using a genetic algorithm to breed normalized postfix expressions," IEEE Trans. Evol. Comput. , vol. 6, no. 4, pp. 390–401, Aug. 2002.