Power Aware High Level Synthesis with Gated Clock Skew Management
T Devimeena1 and V Saravanan2. Article: Power Aware High Level Synthesis with Gated Clock Skew Management. IJCA Proceedings on International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences ICIIIOES(1):34-36, December 2013. Full text available. BibTeX
@article{key:article,
author = {T. Devimeena1 and V. Saravanan2},
title = {Article: Power Aware High Level Synthesis with Gated Clock Skew Management},
journal = {IJCA Proceedings on International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences},
year = {2013},
volume = {ICIIIOES},
number = {1},
pages = {34-36},
month = {December},
note = {Full text available}
}
Abstract
A new method of achieving the target output with a less number of clock pulses has been introduced. Clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits. Although the word signal has a number of other meanings, the term here is used for "transmitted energy that can carry information". In some cases, more than one clock cycle is required to perform a predictable action. As the circuits become more complex, the problem of supplying accurate and synchronized clocks to all the circuits becomes increasingly difficult. A hierarchical low power module approach is utilized for near optimal results. A clock gating architecture can be added with the clock scheduling scheme to control the unnecessary power flow between the idle sequential circuits. The overall power reduction can be calculated by implementing the clock scheduling and power gating techniques in a SRAM Memory architecture with static and dynamic power calculation.
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