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Call for Paper - May 2015 Edition
IJCA solicits original research papers for the May 2015 Edition. Last date of manuscript submission is April 20, 2015. Read More

Design of Efficient Low Power Stable 4-Bit Memory Cell

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IJCA Proceedings on International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences
© 2013 by IJCA Journal
ICIIIOES - Number 1
Year of Publication: 2013
Authors:
K. Gavaskar
S. Priya

K Gavaskar and S Priya. Article: Design of Efficient Low Power Stable 4-Bit Memory Cell. IJCA Proceedings on International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences ICIIIOES(1):1-6, December 2013. Full text available. BibTeX

@article{key:article,
	author = {K. Gavaskar and S. Priya},
	title = {Article: Design of Efficient Low Power Stable 4-Bit Memory Cell},
	journal = {IJCA Proceedings on International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences},
	year = {2013},
	volume = {ICIIIOES},
	number = {1},
	pages = {1-6},
	month = {December},
	note = {Full text available}
}

Abstract

Memory is the most common part in CMOS IC's applications. The power consumption and speed of SRAMs are important issue that has led to multiple designs with the purpose of minimizing the power consumption during both read and write operations. In this paper, a novel 9T static random access memory (SRAM) cell design which consumes less dynamic power and has high read stability is predicted. This paper also includes the SRAM array structure, it consist of sense amplifier and address decoders. The Tanner EDA tool is used for observe the schematic solution at different technologies. Based on the results obtained when compared with the existing methods, by utilizing the above proposed method it is clearly observed that there is a decrease in power consumption and stability improvement of the memory cells.

References

  • S. Borkar, T. Karnik, S. Narendra, J. T schanz, A. Keshavarzi, and V. de, Parameter Variations and Impact on Circuits & Micro architecture," Proceedings of Design Automation Conference. , pp. 338-342, Jun. 2003.
  • A. J. Bhavnagarwala, X. Tang, and J. Meindl,The simpact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability," IEEE Journal of Solid State Circuits, vol. 36, No. 4, pp. 658-665,April 2001.
  • S. Mukhopadhyay, H. Mahmoodi, and K. Roy,Modeling and estimation of failure probability due to parameter variations in nano-scale SRAMs for yield enhancement," In VLSI circuit Symposium, 2004.
  • K. Agarwal, and S. Nassif, Statistical analysis of SRAM stability," Proceedings of 43rd Annual Conference on Design Automation,pp. 57, 2006.
  • E. Seevinck, F. J. List, and J. Lohstroh, Static Noise Margin Analysis of MOS SRAM cells, "IEEE Journal of Solid State Circuits, vol. 22, No. 5, pp. 748-754, Oct. 1987.
  • J. Lohstroh, E. Seevinck, and J. de Groot, Worst-case static noise margin criteria for logic circuits and their mathematical equivalence, "IEEE Journal of Solid State Circuits, vol. SC-18,No. 6, pp. 803-807, Dec. 1983.
  • L. Chang, R. K. Montoye, Y, Nakamura, K. A. Batson, R. J. Eickemeyer, R. H. Dennard, W. Haensch, and D. Jamsek, An 8T SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches," IEEE Journal of Solid State Circuits, vol. 43, No. 4,pp. 956-963, April 2008.
  • S. Lin, Y. B. Kim, and F. Lombardi, A Highly Stable Nanometer Memory for Low-Power Design," Proceeding of IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems, pp. 17-20, 2008.
  • Z. Liu, and V. Kursun, Characterization of a Novel Nine-Transistor SRAM Cell," IEEETransactions on Very Large Scale Integration (VLSI) Systems, vol. 16, No. 4, pp. 488-492,April 2008.
  • K. Agarwal, and S. Nassif, The Impact of Random Device Variations on SRAM Cell stability in Sub-90-nm CMOS Technologies," IEEE Transactions on Very Large Scale Integration (VLSI)Systems, vol. 16, No. 1, pp. 86-97, Jan 2008.
  • Neil H. E. Weste, Kamran Eshraghian, Principles of CMOS VLSI Design, Pearson Education, Inc. ,Singapore, 2002.
  • Sung-Mo Kang, Yusuf Leblebici, CMOS Digital Integrated Circuits, McGraw-Hill Companies,Inc. , New York, 2003.
  • Dake Liu, and Christer Svenson, Power Consumption Estimation in CMOS VLSI Chips, "IEEE Journal of Solid State Circuits, vol. 29,No. 6, pp. 663-670, June 1994.