FPGA Implementation of Pipelined Architecture for RC5
Rakesh Bhimannavar and Jayashree H V. Article: FPGA Implementation of Pipelined Architecture for RC5. IJCA Proceedings on National Conference on Growth of Technologies in Electronics, Telecom and Computers - India's Perception GTETC-IP:16-19, May 2014. Full text available. BibTeX
@article{key:article,
author = {Rakesh Bhimannavar and Jayashree H V},
title = {Article: FPGA Implementation of Pipelined Architecture for RC5},
journal = {IJCA Proceedings on National Conference on Growth of Technologies in Electronics, Telecom and Computers - India's Perception},
year = {2014},
volume = {GTETC-IP},
pages = {16-19},
month = {May},
note = {Full text available}
}
Abstract
Transferring the data more securely plays a vital role in today's communication world. Ensuring that the data transferred is secure is a challenge. It is necessary to make sure that information is hidden from anyone for whom it is not intended. Cryptographic algorithms are extensively used to assure the privacy of the data by providing required security through encryption. Encryption is carried out by performing multiple iterations of complex mathematical operations on the given data using a secret key, such that original data is hard to retrieve unless the secret is known. This paper describes the RC5 algorithm, which is one of the methods to provide security to the data. It involves the use of encryption and decryption processes. The main goal of this paper is to show that the exchange of information is secure in a very strong sense. In this paper a reconfigurable RC5 algorithm for crypto system is implemented in Xilinx Spartan - 6 FPGA with a pipeline scheme. The design has been described in VHDL. This architecture reduces the required hardware resources compared to previous works [9] and achieves high-speed performance.
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