Design of High Speed Full Adder using Improved Differential Split Logic Technique for 130nm Technology and its Implementation in making ALU
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10.5120/16898-6952 |
Gurleen Kaur, Arvind Kumar and Jatinder Singh. Article: Design of High Speed Full Adder using Improved Differential Split Logic Technique for 130nm Technology and its Implementation in making ALU. International Journal of Computer Applications 96(18):40-47, June 2014. Full text available. BibTeX
@article{key:article,
author = {Gurleen Kaur and Arvind Kumar and Jatinder Singh},
title = {Article: Design of High Speed Full Adder using Improved Differential Split Logic Technique for 130nm Technology and its Implementation in making ALU},
journal = {International Journal of Computer Applications},
year = {2014},
volume = {96},
number = {18},
pages = {40-47},
month = {June},
note = {Full text available}
}
Abstract
Adders are the main components in digital designs which are used not only for addition but can be used for multiplication and division too. Adders find use in very large scale integrated circuits from processors (like in arithmetic logic circuits) to application specific integrated circuits. At the same time, high speed computation has become the important part of any digital applications today though low power is a key factor too. In this paper, a high speed full adder using improved differential split logic (DSL) technique is used. We further implement it in 1bit arithmetic logic circuit (ALU). Measurements show that proposed full adder is better than DSL full adder in terms of speed, and further implementation of it in ALU shows that it is better than CMOS ALU in terms of speed, power and power delay product (PDP).
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