An Efficient Design of 2:1 Multiplexer and Its Application in 1-Bit Full Adder Cell
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10.5120/4930-7161 |
Ila Gupta, Neha Arora and B P Singh. Article: An Efficient Design of 2:1 Multiplexer and Its Application in 1-Bit Full Adder Cell. International Journal of Computer Applications 40(2):31-36, February 2012. Full text available. BibTeX
@article{key:article,
author = {Ila Gupta and Neha Arora and B. P. Singh},
title = {Article: An Efficient Design of 2:1 Multiplexer and Its Application in 1-Bit Full Adder Cell},
journal = {International Journal of Computer Applications},
year = {2012},
volume = {40},
number = {2},
pages = {31-36},
month = {February},
note = {Full text available}
}
Abstract
A multiplexer, sometimes referred to as a "mux", is a device that selects between a numbers of input signals. It is a combinational logic circuit. It is a unidirectional device and used in any application in which data must be switched from multiple sources to a destination. This paper represents the simulation of different 2:1 Multiplexer Structures and their comparative analysis on different parameters such as power supply voltage, operating frequency, temperature and area efficiency etc and its application in 1 bit full adder cell. All the simulations have been carried out on BSIM 3V3 90nm technology at Tanner EDA tool.
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