Design optimization of Reversible Logic Universal Barrel Shifter for Low Power applications
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10.5120/5057-7379 |
Ravish Aradhya H V, Lakshmesha J and Muralidhara K N. Article: Design optimization of Reversible Logic Universal Barrel Shifter for Low Power applications. International Journal of Computer Applications 40(15):26-34, February 2012. Full text available. BibTeX
@article{key:article,
author = {Ravish Aradhya H V and Lakshmesha J and Muralidhara K N},
title = {Article: Design optimization of Reversible Logic Universal Barrel Shifter for Low Power applications},
journal = {International Journal of Computer Applications},
year = {2012},
volume = {40},
number = {15},
pages = {26-34},
month = {February},
note = {Full text available}
}
Abstract
Applications such as address generation, encoding, decoding, data shifting, etc are of primary importance in many computing and processing applications. Design of Barrel shifters therefore demands more attention and the advent of quantum computation and reversible logic, design and implementation of all sub-systems in reversible logic has received more attention. Moore’s law in VLSI designs today is no more a simple reality, the device dimensions are shrinking exponentially and the circuit complexity is growing exponentially. Various low power design techniques are proposed and successfully achieved. Device scaling is limited by the power dissipation; and demands better power optimizations methods. Techniques like Energy recovery, Reversible Logic are becoming more and more prominent special optimization techniques in Low Power VLSI designs. Reversible logic opens tremendous avenues for power optimizations in the areas such as Quantum Computing, Nanotechnology, Sprintronics and Optical Computing. Reversibility plays an important role when energy efficient computations are to be designed. The objective of this work is to design a Universal Reversible Barrel Shifter that performs shifting left, right, rotates left and right. The performance characteristics of the existing design and the proposed design are compared with respect to transistor cost, Garbage outputs and Quantum Cost. The performance characteristics analysis is carried out in cadence digital design environment and CMOS implementation in cadence virtuoso.
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