FPGA Based Design and Implementation of Higher Order FIR Filter using Improved DA Algorithm
|
10.5120/4433-6173 |
Addanki Purna Ramesh, G Nagarjuna and Siva G Raam. Article: FPGA Based Design and Implementation of Higher Order FIR Filter using Improved DA Algorithm. International Journal of Computer Applications 35(9):45-54, December 2011. Full text available. BibTeX
@article{key:article,
author = {Addanki Purna Ramesh and G. Nagarjuna and G. Siva Raam},
title = {Article: FPGA Based Design and Implementation of Higher Order FIR Filter using Improved DA Algorithm},
journal = {International Journal of Computer Applications},
year = {2011},
volume = {35},
number = {9},
pages = {45-54},
month = {December},
note = {Full text available}
}
Abstract
Aerospace applications contain accelerometers that are realized with FIR filter using DA (distributed arithmetic) algorithm. When the DA algorithm is directly applied in FPGA to realize FIR filter, it is difficult to achieve the best configuration in the coefficient of FIR filter i.e. the storage resource and the computing speed. To overcome the above difficulty we proposed an improved DA algorithm. This algorithm uses splitted LUTS which results usage of small memory and operational speed increases. The specifications of decimation FIR filter will be derived from the specifications of a third-order single bit sigma-delta modulator. We propose higher order decimation FIR filter i.e. 48th order implementing with less hard ware complexity. The hardware model for the filter was realized using verilog HDL.
References
- Shunwen Xiao,Yajun Chen, “The Design of FIR Filter Base on Improved DA Algorithm and its FPGA Implementation”,Peng Luo College of Physics and Electronic information China West Normal University, CWNU Nanchong, Sichuan, 637002, P.R.China..
- L. Wei, R. J. Yang, X. T. Cui, “Design of FIR filter based on distributed arithmetic and its FPGA implementation, ” Chinese Journal of Scientific Instrument, 2008, vol. 29, pp. 2100-2104.
- L. Zhao, W. H. Bi, F. Liu, “Design of digital FIR band pass filter using distributed algorithm based on FPGA,” Electronic Measurement Technology, 2007,vol. 30, pp.101-104.
- Lukas Fujcik , Thibault Mougel , Jiri Haze and Radimir Vrba , “Modeling and design of novel architecture of multibit switched-capacitor sigma-delta converter with two-step quantization process”, Proceedings of the International conference on Networking,Systems, Mobile communication and Learning Technologies (ICNICONSMCL’06), 2006.
- Patrick Longa and Ali Miri, “Area-Efficient FIR Filter Design on FPGAs using Distributed Arithmetic”, IEEE International Symposium on Signal Processing and Information Technology, pp.248-252, June 2006.
- Uwe Meyer-Base, “Digital Signal Processing with Field Programmable Gate Arrays”,Springer International, ISBN: 81-8128-455-0, 2004.
- Y. T. Xu, C. G. Wang, J. L. Wang, “Hardware Implementation of FIR Filter Based on DA Algorithm,” Journal of PLA University of Science and Technology, 2003, vol. 4, pp. 22-25.
- Sangil Park,”Principle of Sigma-Delta Modulation for Analog-to-Digital Converters”,APR8/D,Rev.1, Motorola Digital Signal Processors,2000
- Matthew P. Donadio“CIC Filter Introduction” m.p.donadio@ieee.org18 July 2000
- D. Wu, Y. H. Wang, H. Z. Lu,“ Distributed Arithmetic and its Implementation in FPGA,” Journal of National University of Defense Technology, 2000, vol. 22, pp.16-19.
- Steven R.Norsworthy, Richard Schrerier and Garbor C.Temes, “Delts-Sigma Data Converters. Theory, Design, and Simulation”, IEEE Press, A John Wiley & Sons, INC. Publication, ISBN: 0-7803-1045-4, 1997. Richard Schreier and Gabor C. Temes, “Understanding Delta-Sigma Data Converters”, IEEE Press, A John Wiley & Sons, INC. Publication, 1996
- G. R. Goslin, “A Guide to Using Field Programmable Gate Arrays (FPGAs) for Application-Specific Digital Signal Processing Performance”, XILINX, 1995
- Sangil Park, “Multistage Decimation Filter Design Technique for High-Resolution igma Delta A/D converters”, IEEE Transactions on Instrumentation and Measurement, VOL41, N o.6, 1991
- Stanley A. White “Applications of Distributed arithmetic to digital signal processing tutorial review”, IEEE ASSP Magazine 1989.
- Eugene B.Hogenauer, “An Economical Class of Digital Filters for Decimation and Interpolation”, IEEE Transactions on Acoustics and Signal processing, VOL, ASSP-29,No.2, pp 155-162, 1981
- Basic Principles of Operation and Applications of the Accelerometer. Paschal Meehan and Keith Moloney - Limerick Institute of Technology.