Analysis of the Effect of Temperature Variations on Sub-threshold Leakage Current in P3 and P4 SRAM Cells at Deep Sub-Micron CMOS Technology
|
10.5120/4395-6101 |
Rajesh Singh, Debasis Sahu, Neeraj Kr. Shukla, Pulkit Bhatnagar, Geetanjali and Ankit Goel. Article: Analysis of the Effect of Temperature Variations on Sub-threshold Leakage Current in P3 and P4 SRAM Cells at Deep Sub-Micron CMOS Technology. International Journal of Computer Applications 35(5):8-13, December 2011. Full text available. BibTeX
@article{key:article,
author = {Rajesh Singh and Debasis Sahu and Neeraj Kr. Shukla and Pulkit Bhatnagar and Geetanjali and Ankit Goel},
title = {Article: Analysis of the Effect of Temperature Variations on Sub-threshold Leakage Current in P3 and P4 SRAM Cells at Deep Sub-Micron CMOS Technology},
journal = {International Journal of Computer Applications},
year = {2011},
volume = {35},
number = {5},
pages = {8-13},
month = {December},
note = {Full text available}
}
Abstract
With ever increasing power density and temperature variations within high density VLSI chips, it is very important to study the temperature effects on the devices in a compact way and to predict their scaling. In this paper, the sub-threshold leakage power analysis of the P3 and P4 SRAM cells has been carried out at a temperature range from -250C to +1250C. It has been observed that the sub-threshold leakage and the standby power dissipation increases with increase in temperature. However, due to the stacked pMOS design used in P4 and P3 SRAM cells, minimum sub-threshold leakage and standby leakage power is observed as compared to the conventional 6T design.
References
- International Technology Roadmap for Semiconductors-2003. Online-Available at http://www.publicitrs.net.
- K. Cao, W.-C Lee, W. Liu, X. Jin, P. Su, S. Fung, J. An, B. Yu, and C. Hu, “BSIM4 gate leakage model including source drain partition,” Tech. Dig. Int. Electron Devices Meeting, 2000, pp. 815–818.
- Neeraj Kr. Shukla, Shilpi Birla, R.K. Singh, and Manisha Pattanaik, “Speed and Leakage Power Trade-off in Various SRAM Circuits”, International Journal of Computer and Electrical Engineering (IJCEE), Singapore, Vol.3, No.2, Apr. 2011, pp. 244-249.
- Sung-Mo Kang, Yusuf Leblebici, “CMOS Digital Integrated Circuits-Analysis and Design”, Third Edition Tata McGraw-Hill Edition, New Delhi, India.
- Kaushik Roy, Saibal Mukhopadhyay and Hamid Mahmoodi-Meimand, “Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits”, Proceedings of the IEEE, Vol. 91, No. 2, February 2003, pp. 305-327.
- J. M. Rabaey, Digital Integrated Circuits. Englewood Cliffs, NJ: Prentice-Hall, 1996, ch. 2, pp. 55–56.
- Fundamentals of Modern VLSI Devices. New York: Cambridge Univ. Press, 1998, ch. 3, pp. 120–128.
- R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, “Design of ion-implanted MOSFETs with very small physical dimensions,” IEEE J. Solid-State Circuits, vol. SC-9,pp. 256, 1974.
- G. Razavipour,A. Afzali-Kusha and M. Pedram,”Design and Analysis of Two Low-Power SRAM Cell Structures”,IEEE Transaction on VLSI systems,Vol. 17,No. 10,Oct. 2009,pp. 1551-1555.
- Neeraj Kr. Shukla, R.K Singh, Manisha Pattanaik , “Design and Analysis of a Novel Low-Power SRAM Bit-Cell Structure at Deep-Sub-Micron CMOS Technology for Mobile Multimedia Applications”, International Journal of Advanced Computer science and Applications (IJACSA), vol. 2-No.5, pp. 43-49, 2011.
- Neeraj Kr. Shukla, R.K Singh, Manisha Pattanaik, “A Novel Approach to Reduce the Gate and Sub-threshold Leakage in a conventional SRAM Bit-cell Structure at Deep-Sub Micron CMOS Technology,” International Journal of Computer Applications (IJCA), vol. 23-No.7, pp. 23-28, June 2011.