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VHDL-AMS modelling and Optimization of a Fractional-N Synthesizer with experiment Designs
International Journal of Computer Applications
© 2011 by IJCA Journal
Volume 33 - Number 8
Year of Publication: 2011
|
10.5120/4041-5790 |
S Sahnoun, N Masmoudi and H Levi. Article: VHDL-AMS modelling and Optimization of a Fractional-N Synthesizer with experiment Designs. International Journal of Computer Applications 33(8):24-27, November 2011. Full text available. BibTeX
@article{key:article,
author = {S. Sahnoun and N. Masmoudi and H. Levi},
title = {Article: VHDL-AMS modelling and Optimization of a Fractional-N Synthesizer with experiment Designs},
journal = {International Journal of Computer Applications},
year = {2011},
volume = {33},
number = {8},
pages = {24-27},
month = {November},
note = {Full text available}
}
Abstract
In this work, we expose our approach to design and optimize mixed analogue and digital systems at a high level description using the hardware description language VHDL-AMS. Many statistical experimental design methods are employed in optimization. We apply Hocke_D4 experimental designs with five parameters in order to minimize the lock time and the spurious level of a fractional-N synthesizer acting as a direct MSK modulator and designed for the DECT standard application.
Reference
- IEEE Standard VHDL “Analog and Mixed Signal Extensions”, IEEE Std 1076.1–1999, IEEE, New-York, 1999.
- Y. Hervé, A. Fakhfakh, “Requirements and Verifications through an extension of VHDL-AMS”, FDL04, September 2004, Lille, France.
- S. Snaidero « Modélisation multidisciplinaire VHDL-AMS de systèmes complexes: vers le Prototypage Virtuel » PhD thesis, december 2004.
- E. Temporitit, et. al, "A 700kHz Bandwidth SD Fractional Synthesizer With Spurs Compensation and Linearization Techniques for WCDMA Applications," IEEE J. Solid-State Circuits, vol. 39, pp. 1446-1454, Sept. 2004.
- M. Henderson Perrott, « Techniques for high data modulation and low power operation of fractional-N frequency synthesizers », PhD thesis, 1997.
- A Calaci et al, “Systematic Analysis & Optimization of Analog/Mixed-Signal Circuits Balancing Accuracy and Design Time”, SBCCI’10, September 6-9, 2010, Sao Paulo, SP, Brazil.
- G Strube, “Robuste Verfahren zur Worst-Case-und-Ausbute-Analyse analog integrierter Schaltungen”, Hieronymus Munchen, 1998, ISBN 3-933083-52-4.
- Guo Yu, Peng Li “Yield-Aware Hierarchical Optimization of Large Analog Integrated Circuits”, 978-1-4244-2820-5/08/$25.00 ©2008 IEEE.
- D Banerjee, D Brown, K Nguyen “Loop Filter Optimization”,www.national.com/AU/design/loop_filter_optimization.pdf.
- Michael H. Perrott “PLL Design Using the PLL Design Assistant Program” http://www.cppsim.com July 2008.
- M Michael, S Neophytou “Cadence Encounter™ RTL Compiler Ultra”, Nicosia, Spring 2007.
- Antonio J. Lopez Martin “Tutorial Cadence Design Environment”, Klipsch School of Electrical and Computer Engineering New Mexico, State University, October 2002.
- M. H. Perrott, Theodore L. Tewksbury III, Charles G. Sodini, «A 27-mW CMOS Fractional- Synthesizer Using Digital Compensation for 2.5-Mb/s GFSK Modulation», IEEE journal of solid-state circuits, vol. 32, no. 12, december 1997.
- C. Fourtet «Modulation double port FSK/GFSK pour une utilisation en DECT ou liens radio digitaux» Motorola Semiconducteurs S.A. Centre Electronique de Toulouse.
- S Eloued, A Fakhfakh and N Masmoudi “ Analogue synthesis methodology using VHDL-AMS application to a frequency synthesizer design”, Transactions on Systems, Signals and Devices (TSSD), Vol. 4, No. 4, pp 591, 2009.
- Simplorer reference manual, 2003.
- E. P. Box, W. G. Hunter and J. S. Hunter, “Statistics for Experimenters”, Wiley, New York, 1978.
- D. Mathieu, J. Nony, R. Phan-Tan-Luu, ”NEMROD-W software”, LPRAI, Marseille, 2000.