Design of Area and Power Efficient Modified Carry Select Adder
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10.5120/3999-5666 |
Sarabdeep Singh and Dilip Kumar. Article: Design of Area and Power Efficient Modified Carry Select Adder. International Journal of Computer Applications 33(3):14-18, November 2011. Full text available. BibTeX
@article{key:article,
author = {Sarabdeep Singh and Dilip Kumar},
title = {Article: Design of Area and Power Efficient Modified Carry Select Adder},
journal = {International Journal of Computer Applications},
year = {2011},
volume = {33},
number = {3},
pages = {14-18},
month = {November},
note = {Full text available}
}
Abstract
Adders are one of the widely used digital components in digital integrated circuit design. The Carry Select Adder (CSA) provides a good compromise between cost and performance in carry propagation adder design. However, conventional CSA is still area-consuming due to the dual ripple carry adder (RCA) structure. In this paper, modification is done at gate-level to reduce area and power consumption. The Modified Carry Select-Adder (MCSA) is designed for 8-bit, 16-bit, 32-bit and 64-bit and then compared with conventional CSA respective architectures. MCSA shows reduction in area and power consumption in comparison with conventional CSA with small increase in delay.
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