Characterization of PNN Stack SRAM Cell at Deep Sub-Micron Technology with High Stability and Low Leakage for Multimedia Applications
|
10.5120/3984-5627 |
R.K.Singh, Shilpi Birla and Manisha Pattanaik. Article: Characterization of PNN Stack SRAM Cell at Deep Sub-Micron Technology with High Stability and Low Leakage for Multimedia Applications. International Journal of Computer Applications 33(1):13-17, November 2011. Full text available. BibTeX
@article{key:article,
author = {R.K.Singh and Shilpi Birla and Manisha Pattanaik},
title = {Article: Characterization of PNN Stack SRAM Cell at Deep Sub-Micron Technology with High Stability and Low Leakage for Multimedia Applications},
journal = {International Journal of Computer Applications},
year = {2011},
volume = {33},
number = {1},
pages = {13-17},
month = {November},
note = {Full text available}
}
Abstract
The explosive growth of battery operated devices has made low-power design a priority in recent years Moreover, embedded SRAM units have become an important block in modern SoCs. Present day SRAMs are striving to increase bit counts while maintaining low power consumption and high performance. To achieve these objectives there is a need of continuous scaling of CMOS transistors, and so the process technology scaling and need for better performance enabled embedding of millions of Static Random Access Memories (SRAM) cells into modern-day ICs. In several applications, the embedded SRAMs can occupy the majority of the chip area and contain hundreds of millions of transistors. As the process technology continues to scale deeper into the nanometer region, the stability of embedded SRAM cells is a growing concern. The supply voltage must scale down accordingly to control the power consumption and maintain the device reliability. Scaling the supply voltage and minimum transistor dimensions that are used in SRAM cells challenge the process and design engineers to achieve reliable data storage in SRAM arrays. This task is particularly difficult in large SRAM arrays that can contain millions of bits .In this paper we proposed a novel 9T SRAM cell with the objective to increase the stability and reduce the leakage for multimedia mobile applications at deep submicron level. All the Simulations are done at 45nm technology.
Reference
- A. Bhavnagarwala, X. Tang, and J. Meindl, “ The impact of intrinsic device fluctuations on CMOS SRAM cell stability”. IEEE Journal of Solid-State Circuits (JSSC), 36:658–665, April 2001.
- F. Yang, J. Hwang, and Y. Li., “Electrical characteristic fluctuations in sub-45 nm CMOS devices”. In Proc. of IEEE Custom Integrated Circuits Conference CICC, pages 691–694, September 2006.
- F. Lai and C. Lee., “On-chip voltage down converter to improve SRAM read-write margin and static power for sub-nano CMOS technology”. IEEE Journal of Solid-State Circuits (JSSC), 42:2061–2070, September 2007.
- Sinangil M., Naveen Verma, A.P.Chandrakasan, “ A Reconfigurable 8T Ultra –Dynamic Voltage Scalable( U-DVS ) SRAM in 65nm CMOS” , Solid-State Circuits, IEEE Journal ,vol. 44 , no. 11,Nov.2009, pp.3163-3173.
- Zhiyu Liu and Volkan Kursun, “Characterization of a Novel Nine-Transistor SRAM cell”, IEEE Transaction of Very large Scale Integration Systems, vol. 16, NO. 4, April 2008,pp.488-492
- Sheng Lin, Yong-Bin Kim , Fabrizio Lombardi., “Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability” Integration the VLSI Journal, vol. 43 ,January 2010, pp. 176-187.
- Zheng Guo, Andrew Carlson, Liang-Teck Pang, Kenneth Duong, Tsu-Jae King Liu, Borivoje Nikolic, “Large-Scale Read/Write Margin Measurement in 45nm CMOS SRAM Arrays”,IEEE Symposium on VLSI Circuits Digest of Technical Papers 2008,pp-42-43.
- Jiajing Wang, Satyanand Nalam, and Benton H. Calhoun,“Analyzing Static and Dynamic Write Margin for Nanometer SRAMs”, ISPLED 2008,pp.129-134.
- E. Seevinck et al., “Static-noise margin analysis of MOS SRAM cells,”IEEE J. Solid-State Circuits, vol. SC-22, no. 5, pp. 748–754, Oct. 1987.
- Evelyn Grossar, Michele Stucchi, Karen Maex,” Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies”, Solid-State Circuits, IEEE Journal ,vol. 41 , no. 11, Nov.2006, pp.2577-2588.
- Shilpi Birla, Manisha Pattanaik, R.K.Singh “Static Noise Margin Analysis of Various SRAM Topologies”, IACSIT International Journal of Engineering and Technology, Vol.3, No.3, June 2011,pp-304-309
- Shilpi Birla, Neeraj Kr. Shukla, Manisha Pattanaik, R.K.Singh, “Device and Circuit Design Challenges for Low Leakage SRAM for Ultra Low Power Applications”, Canadian Journal on Electrical & Electronics Engineering Vol. 1, No. 7, December 2010.
- Benton H. Calhoun Anantha P. Chandrakasan “Static Noise Margin Variation for Sub-threshold SRAM in 65 nm CMOS”, Solid-State Circuits, IEEE Journal vol. 41, Jan.2006, Issue 7, pp.1673-1679.