A Novel Design of SET-CMOS Half Subtractor and Full Subtractor
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10.5120/20032-2134 |
Fathima A Thuslim. Article: A Novel Design of SET-CMOS Half Subtractor and Full Subtractor. International Journal of Computer Applications 114(12):33-37, March 2015. Full text available. BibTeX
@article{key:article,
author = {A. Fathima Thuslim},
title = {Article: A Novel Design of SET-CMOS Half Subtractor and Full Subtractor},
journal = {International Journal of Computer Applications},
year = {2015},
volume = {114},
number = {12},
pages = {33-37},
month = {March},
note = {Full text available}
}
Abstract
Single Electron transistor have high integration density, ultra-low power dissipation, ultra-small size, unique coulomb blockade oscillation characteristics which makes an attractive technology for future low power VLSI/ULSI systems. The Single Electron Transistor have extremely poor driving capabilities so that direct application to practical circuits is a yet almost impossible, to overcome this problem and to investigate the robustness and fastness of the novel design, the hybrid circuits of SET and CMOS are builded. In this work, novel design of SET-CMOS of Half Subtractor and Full Subtractor circuits are designed.
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