10.5120/18971-0428 |
Ravi Khatwal and Manoj Kumar Jain. Article: MIPS Integrated Architectural Memory Design Synthesis for Low Power Embedded Devices. International Journal of Computer Applications 108(13):13-23, December 2014. Full text available. BibTeX
@article{key:article, author = {Ravi Khatwal and Manoj Kumar Jain}, title = {Article: MIPS Integrated Architectural Memory Design Synthesis for Low Power Embedded Devices}, journal = {International Journal of Computer Applications}, year = {2014}, volume = {108}, number = {13}, pages = {13-23}, month = {December}, note = {Full text available} }
Abstract
Recently high performance and low power consumption custom memory design system is the crucial innovation for wireless embedded devices. In this paper we have implemented MIPS based memory architectural design and analyze its simulation efficiency. Low power and high performance embedded devices such as mobile, wifi devices implemented with MIPS architecture design that reduces the access time and increases the system performance. Existing CAM cell design also reduces the access time as in efficient manner. We have analyzed CAM architecture design with xup-5 FPGA environments and analyze CAM cell efficiency. MIPS RF memory has implemented for various high performances ASIP design architecture and embedded devices.
References
- Jain, M. K. , Balakrishnan, M. and Kumar A. , 2005. Integrated on-chip storage evaluation in ASIP synthesis, In Proceeding of 18th International Conference on VLSI design, 274 – 279.
- Kuldar, M. , Fan, K. , Chu, M. and Mahlke, S. 2004. Automatic Synthesis of Customized Local Memories for Multiclustered Application Accelerators, In Proceeding of 15th IEEE International Conference on Application –Specific Systems, Architectures and Processors. 304-314.
- Vahid, F. , Stitt, G. , Guo, Z. , Najjar, W. 2005. Technique for Synthesizing Binaries to an advanced Register/Memory Structure, SIGA 13th International symposium on FPGA (2005). 118-124.
- Xilinx tool [online] Available: www. xilinx. com/homepage/.
- P. Meloni, S. Pomato, G. Tuveri, L. Raffo, M. Lindwer, "Enabling fast ASIP design space exploration: An FPGA based runtime reconfigurable prototype". Hindawi Publication Cooperation Journal of VLSI design (2012).
- Prikryl, Z. , Kroustek, I. , Hruska, T. , Kolar, D. Fast just in time translated simulator for ASIP. Design and diagnostics of electronic circuits and system (DDECS), 2011, IEEE 14TH international symposium. 279-282.
- P. Meloni, S. Pomato, R. Piscitelli, L. Raffo, M. Lindwer. Combining on-hardware prototyping and high level simulation for DSE of multi-ASIP system. IEEE Embedded Computer Systems (SAMOS), (2012). 310-317.
- Jordans, R. , Diken, E. , Jozwiak, L. , Corporaul, H. (2014). Build master: efficient ASIP architecture exploration through compilation and simulation result caching. IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems,. (2014). 83-88.
- C. K. Lai, Y. J. Huang and J. F. Lia. "Self-Repair Technique for Content Addressable Memories with Address-Input-Free Writing Function", Journal of information science and engineering. (2013). 493-507.
- Ozer, E. , Sendag, R. and Gregg, D. 2005. Multiple-Valued Caches for Power-Efficient Embedded Systems. In Proc of the 35th International Symposium on Multiple-Valued Logic (ISMVL'05) (2005).
- Wang, P. , Sung, G. , Wang, T. , Xie, Y. , Cong, J. (2013). Designing Scratchpad Memory Architecture with Emerging STT-RAM Memory Technologies. Circuits and system (ICACS) (2013) 1244-1247.