Simulation and Synthesis of Majority Logic Decoder/Detector for EG-LDPC Codes
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10.5120/18225-9376 |
Chinna Babu.j, S.prathyusha and Usha V Sree. Article: Simulation and Synthesis of Majority Logic Decoder/Detector for EG-LDPC Codes. International Journal of Computer Applications 104(8):32-35, October 2014. Full text available. BibTeX
@article{key:article,
author = {Chinna Babu.j and S.prathyusha and V. Usha Sree},
title = {Article: Simulation and Synthesis of Majority Logic Decoder/Detector for EG-LDPC Codes},
journal = {International Journal of Computer Applications},
year = {2014},
volume = {104},
number = {8},
pages = {32-35},
month = {October},
note = {Full text available}
}
Abstract
In this paper, a technique was proposed to protect memory cells, which are more susceptible to soft errors. These memory cells are to be protected with effective error correction codes. MLD codes are suitable for memory applications because of their ability to correct large number of errors. Conversely, they increase the average latency of the decoding process because it depends upon the code size that impacts memory performance. A method was proposed as majority logic decoder/detector of Euclidean geometry low density parity check codes(EG-LDPC). BUT this MLDD reduces the decoding time, memory access time and area utilization. In this brief, we obtain the application of MLDD to a class of EG-LDPC. The simulation results show that MLDD consumes less area and speed of execution is high for error detection and correction. On comparison with MLD, MLDD provides high speed of operation with reduced execution time, decreased area and high performance.
References
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