Performance Analysis of Full Adder Circuit using Improved Feed through Logic
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10.5120/17700-8678 |
Sandeep Sangwan and Jyoti Kedia. Article: Performance Analysis of Full Adder Circuit using Improved Feed through Logic. International Journal of Computer Applications 101(7):27-30, September 2014. Full text available. BibTeX
@article{key:article,
author = {Sandeep Sangwan and Jyoti Kedia},
title = {Article: Performance Analysis of Full Adder Circuit using Improved Feed through Logic},
journal = {International Journal of Computer Applications},
year = {2014},
volume = {101},
number = {7},
pages = {27-30},
month = {September},
note = {Full text available}
}
Abstract
In this paper performance analysis of full adder circuit has been carried out using improved feedthrough logic design technique which is a novel design technique. This technique is an improvement over already existing FTL. The circuit has been designed using existing high speed feedthrough logic and improved feedthrough logic in both 90nm and 180nm technology using cadence tools and a comparison has been done for power and delay. full adder circuit using improved FTL dissipates 37. 9% less than full adder using high speed FTL but delay is increased by 15. 13% but the overall power delay product is reduced by 28. 5%.
References
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